STLS2F Loongson 2F high performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock frequency. Loongson 2F: High performance bit superscalar MIPS. ® microprocessor. Features. □ bit superscalar architecture. □ MHz clock. ICT Loongson 2F (ST STLS2F01) (Godson-2). ICT Loongson 2F ( MHz) (90 nm) + MB of DDR2. Lemote YeeLoong notebook. 4-way superscalar.

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It may also loonhson the data directly from one of the result buses if its source register number matches the destination register number of the result bus. Archived from the original on 21 June Early implementations of the family lacked four instructions patented by MIPS Technologies to avoid legal issues.

Loongson – LinuxMIPS

Most common open-source applications including OpenOffice. Retrieved 26 May From Wikipedia, the free encyclopedia. The value is then sent to memory access queue, where dynamic memory disambiguation and memory forwarding is performed. Views Read Edit View history. It was formerly called Godson. The issued instruction reads its source operands from the physical register file and is sent to the associated functional loongxon. Archived from the original on 17 April A new physical register is allocated for ,oongson logical destination register, and the logical source register is renamed according to the latest physical register allocated for the same logical register.

Based in BeijingBLX focuses on designing the bit Loongson general-purpose and embedded processors, together with developing software tools and reference platforms. The high-performance Dawningwhich has a projected speed of over one quadrillion operations per second, will incorporate the Loongson processor as its core. By using this site, you agree to the Terms of Use and Privacy Policy.


Archived from the original on 9 May When there are multiple instructions ready for the same functional unit, the oldest one is selected. This list is incomplete ; you can help by expanding it. Archived from the original on 23 October The highest frequency of Godson-3B is 1.

Loongson 2F 900MHz vs MediaTek MT8163 V/A 1.5 GHz

Loongson is the result of a public—private partnership. They are also sent to the memory access queue to allow committed store instructions to write cache or memory. Inter-instruction dependencies among four instructions mapped in the same cycle are also checked.

Broadcom various Cavium Octeon.

Package: linux-image-loongson-2f (3.16+63+deb8u2)

InLoongson released latest version of 3A cpu, 3A Archived from the original on 25 July This article’s use of external links may not follow Wikipedia’s policies or guidelines. Results of a benchmark test, conducted in Aprilloongson available [14]. Result buses are also sent to the reservation station for snooping and to the register mapping table to notify that the associated physical register is ready.

Up to four instructions can be committed in program order per cycle.

Loongson 2F MHz vs MediaTek MT V/A GHz

The Godson 2F, released to market in earlyran at 1. It is fabricated with 0. One instruction with all required operands ready is selected from the fixed- or floating-point reservation station loongon each functional unit.


Retrieved 16 April Archived from the original on 4 June Li Guojie, chairman of Dawning Information Industry Company and director and academician of the Institute of Computing Technology, said research and development of the Dawning is expected to be completed in two years. Retrieved from ” https: Many operating systems work on Loongson: Open source applications on Linux Platform can be ported with little effort.

The Loongson 3 adds over new instructions over Loongson 2. In other projects Wikimedia Commons. The topic of the speech was “Research and Development of Godson processors”. Instructions are executed according to its type and execution results are written back to the register file. The four instructions in IR are decoded loogson the internal format and sent to the register renaming module. The manufacturer states that poongson user experience of the desktop solution has been significantly improved over its Loongson-3A based predecessor.

In AugustLoongson Technology Corp. June Learn how and when to remove this template message. Each version can be clocked from 1. Each empty entry of reservation stations and queues selects among four dispatched instructions in this cycle. Archived loongsin the original on 15 September Instructions with unready source operands snoop result and forward buses for their operands.

The Loongson 2 adds bit ability to the Loongson architecture.

Last modified: January 4, 2020